1. Field of the Invention
The present invention relates to a data processing apparatus and a shared memory accessing method. More particularly, the invention relates to a video camera acting as a data processing apparatus for processing image data. In having a shared memory structured to include a cache area, a compressed cache area, and a non-cache area which are switched from one to another in a caching process for allowing the single shared memory to be shared by a plurality of function blocks, the invention envisages shortening the time required by each of the function blocks to access the shared memory while reducing the size of a cache memory.
2. Description of the Related Art
Recent years have witnessed the widespread use of a certain type of video equipment such as video cameras that allow a plurality of function blocks to share a single shared memory for processing image data. FIG. 7 is a block diagram showing a typical video camera 1 in which one shared memory 5 is shared by a plurality of function blocks. In the video camera 1, a first, a second and a third function block 2, 3 and 4 share the single memory 5.
The first function block 2 is a data processing circuit that performs such image-related processes as white balance control and gamma correction. The second function block 3 is a data processing circuit that illustratively resizes image data into a size suitable for display on a display section, not shown. The third function block 4 is a data processing circuit that compresses and expands image data illustratively through the use of MPEG (Moving Picture Experts Group) techniques. The video camera 1 acquires image data using an imaging section, not shown, and stores the acquired image data into the shared memory 5 consecutively. The image data placed in the shared memory 5 is processed successively by the first and the second function blocks 2 and 3 for display. In accordance with the user's instructions, the image data processed by the first function block 2 may be processed by the third function block 4 before being recorded to a recording medium, not shown. The video camera 1 may also read image data from the recording medium, place the retrieved image data into the shared memory 5, and have the third and the second function blocks 4 and 3 process the data in the shared memory 5 successively for display.
The first through the third function blocks 2 through 4 are connected to a shared memory controller 6 via a bus. The first through the third function blocks 2 through 4 may each request the shared memory controller 6 to read image data or other resources. In response to the read request, the shared memory controller 6 outputs the requested image data which is then processed by the requesting function block. Each of the first through the third function blocks 2 through 4 may also request the shared memory controller 6 to write image data or the like. In keeping with the response from the shared memory controller 6, the requesting function block outputs the image data of interest to the shared memory controller 6.
In response to a read request from any one of the first through the third function blocks 2 through 4, the shared memory controller 6 reads the requested data from the shared memory 5 and places the read data onto the bus. Responding to a write request from any one of the first through the third function blocks 2 through 4, the shared memory controller 6 writes to the shared memory 5 the data that is input from the request function block. According to the structure outlined in FIG. 7, the memory size is made smaller than if each of the function blocks is furnished with its own memory.
Usually, computers utilize the cache memory scheme for boosting the speed of access to recording media. Japanese Patent Laid-open No. Hei 5-73413 discloses a method whereby the data to be written to a cache memory is compressed in order to reduce the cache memory size.
Illustratively, large quantities of data may come to be processed in the structure of FIG. 7. In such a case, the masses of data exchanged between the shared memory 5 and the shared memory controller 6 may exhaust the bandwidth therebetween. In the structure of FIG. 7, that means it takes so much time to transfer data between one function block and the shared memory controller 6 over the bus that the other function blocks cannot gain access to the shared memory for an extended period of time. As a result, the time required by each of the function blocks to access the shared memory tends to be inordinately prolonged.
One way to solve the problem outlined above is by utilizing a cache memory. However, the simple use of the cache memory scheme entails the disadvantage of a growing cache memory size. The bloated cache memory may be reduced using techniques such as one disclosed in Japanese Patent Laid-open No. Hei 5-73413. This kind of technique tends to require spending a lot of time compressing and expanding the data to be input and output to and from the cache memory. Another way to solve the problem of the massive data transfer between the function blocks and the shared memory controller 6 is by expanding the bandwidth through acceleration of the shared memory 5 and the shared memory controller 6 in operation. This solution, however, involves increasing dissipation of power.